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1 o f 19 features ? 256- bit electrically erasable programmable read only memory (eeprom) plus 64 - bit one - time programmable application register ? unique, factory - lasered and tested 64 - bit registration number (8 - bit family code + 48 - bit serial number + 8 - bit crc tester) assures absolute identity because no two parts are alike ? built - in multidrop controller ensures compatibility with other microlan products ? eeprom organized as one page of 32 bytes for random access ? reduces control, address, data, and po wer to a single data pin ? directly connects to a single port pin of a microprocessor and communicates at up to 15 .3kbits per second ? 8- bit family code specifies ds2430a communication requirements to reader ? presence detector acknowledges when reader first app lies voltage ? low cost to - 92 or 6 - pin tsoc and ucsp surface mount package ? reads and writes over a wide voltage range of 2.8v to 5.25 v from - 40c to +85c ordering information part temp range pin - package ds2430a+ - 40c to +85c 3 to - 92 ds2430a+t&r - 40c to +85c 3 to - 92 (2k pcs) ds2430ap+ - 40c to +85c 6 tsoc ds2430ap+t&r - 40c to +85c 6 tsoc (4k pcs) +denotes a lead (pb) - free /rohs - compliant package. t&r = tape and reel. pin assignment note: the leads of to - 92 packages on tape and reel are formed to approximatel y 100 - mil (2.54 mm) spacing. for details see the package information . pin description to -92 tsoc pin 1 ground ground pin 2 data data pin 3 nc nc pin 4 CCCC nc pin 5 CCCC nc pin 6 CCCC nc ds2430a 256 - bit 1 - wire eeprom side view 1 2 3 6 5 4 top view 3.7mm x 4.0mm x 1.5mm tsoc package bottom view to - 92 dallas ds2430a 2 3 1 1 2 3 19 - 5236; rev 2 /1 2 not recommended for new designs
ds2430a 2 of 19 description the ds2430a 256 - bit 1 - wire ? eeprom identifies and stores relevant information about the product to which it is associated. this lot or product specific information can be accessed with minimal interface, for example a single port pin of a microcontroller. the ds2430a consists of a factory - lasered registr ation number that includes a unique 48 - bit serial number, an 8 - bit crc, and an 8 - bit family code (14h) plus 256 bits of user - programmable eeprom and a 64 - bit one - time programmable application register. the power to read and write the ds2430a is derived ent irely from the 1 - wire communication line. data is transferred serially via the 1 - wire protocol, which requires only a single data lead and a ground return. the 48 - bit serial number that is factory - lasered into each ds2430a provides a guaranteed unique id entity that allows for absolute traceability. the to - 92 and tsoc packages provide a compact enclosure that allows standard assembly equipment to handle the device easily for attachment to printed circuit boards or wiring. typical applications include stor age of calibration constants, board identification, and product revision status. overview the block diagram in figure 1 shows the relationships between the major control and memory sections of the ds2430a. the ds2430a has four main data components: 1) 64 - bit lasered rom, 2) 256 - bit eeprom data memory with scratchpad, 3) 64 - bit one - time programmable application register with scratchpad and 4) 8 - bit status memory. the hierarchical structure of the 1 - wire protocol is shown in figure 2. the bus master must fir st provide one of the four rom function commands: 1) read rom, 2) match rom, 3) search rom, 4) skip rom. the protocol required for these rom function commands is described in figure 8. after a rom function command is successfully executed, the memory funct ions become accessible and the master can provide any one of the four memory function commands. the protocol for these memory function commands is described in figure 6. all data is read and written least significant bit first. 64- bit lasered rom each ds 2430a contains a unique rom code that is 64 bits long. the first 8 bits are a 1 - wire family code (14h). the next 48 bits are a unique serial number. the last 8 bits are a crc of the first 56 bits. (figure 3). the 1 - wire crc is generated using a polynomial generator consisting of a shift register and xor gates as shown in figure 4. the polynomial is x 8 + x 5 + x 4 + 1. additional information about the 1- wire c rc is available in application note 27 . the shift register bits are initialized to 0. then starting with the least significant bit of the family code, one bit at a time is shifted in. after the 8 th bit of the family code has been entered, then the serial number is entered. after the 48 th bit of the serial number has been enter ed, the shift register contains the crc value. shifting in the 8 bits of crc should return the shift register to all 0s. 1 - wire is a registered trademark of maxim integrated products, inc. not recommended for new designs
ds2430a 3 of 19 ds2430a block diagram figure 1 not recommended for new designs
ds2430a 4 of 19 hierarchical structure for 1 - wire protocol figure 2 64- bit lasered rom figure 3 8 - bit crc cod e 48 - bit serial number 8 - bit family code (14h) msb lsb msb lsb msb lsb 1- wire crc generator figure 4 polynomial = x 8 + x 5 + x 4 + 1 not recommended for new designs
ds2430a 5 of 19 memory the memory of the ds2430a consists of three separate sections, called data memory, application register, and status register (figure 5). the data memory and the application register each have its own intermediate storage area called scratchpad that acts as a buffer when writing to the device. the data memory can be read and written as often as desired. the application register, however, is one - time programmable only. once the application register is programmed, it is automatically write protected. the status register indicate s whether the application register is already locked or whether it is still available for storing data. as long as the application register is unprogrammed, the status register read s ffh. copying data from the register scratchpad to the application register clear s the 2 least significant bits of the status register, yielding an fch the next ti me one reads the status register. ds2430a memory map figure 5 memory function commands the memory function flow chart (figure 6) describes the protocols necessary for accessing the different memory sections of the ds2430a. an example is shown later in this document. write scratchpad [0fh] after issuing the write scratchpad command, the master must first provide a 1 - byte address, followed by the data to be written to the scratchpad for the data memory. the ds2430a automatically increment s the address a fter every byte it receive s . after having received a data byte for address 1fh, the address counter wrap s around to 00h for the next byte and writing continues until the master sends a reset pulse. read scratchpad [aah] this command is used to verify data previously written to the scratchpad before it is copied into the final storage eeprom memory. after issuing the read scratchpad command, the master must provide the 1 - byte starting address from where data is to be read. the ds2430a automatically incremen ts the address after every byte read by the master. after the data at address 1fh has been read, the address counter wrap s around to 00h for the next byte and reading continues until the master sends a reset pulse. not recommended for new designs
ds2430a 6 of 19 memory function flow chart figure 6 copy scratchpad [55h] after the data stored in the scratchpad has been verified the master may send the copy scratchpad command followed by a validation key of a5h to transfer data from the scratchpad to the eeprom memory. this command always cop ies the da ta of the entire scratchpad. therefore, if one desires to change only a few bytes of the eeprom data, the scratchpad should contain a copy of the latest eeprom data before the write scratchpad and copy scratchpad commands are issued. after this command an d the validation key are issued, the data line must be held above v pupmin for at least t prog . read memory [f0h] the read memory command is used to read a portion or all of the eeprom data memory and to copy the entire data memory into the scratchpad to prepare for changing a few bytes. to copy data from the data memory to the scratchpad and to read it, the master must issue the read memory command followed by the 1 - byte starting address of the data to be read from the scratchpad. the ds2430a automatically increment s the address after every byte read by the master. after the data of address 1fh has been read, the address counter wrap s around to 00h for the next byte and reading continues until the master sends a reset pulse. if one intends to copy the entire data memory to the scratchpad without reading data, a starting address is not required; the master may send a reset pulse immediately following the command code. not recommended for new designs
ds2430a 7 of 19 memory function flow chart figure 6 (cont inued) write application register [99h] this command is essentially the same as the write scratchpad command, but it addresses the 64 - bit register scratchpad. after issuing the command code, the master must provide a 1 - byte address, followed by the data to be written. the ds2430a automatically increm ent s the address after every byte it receive s . after receiv ing the data byte for address 07h, the address counter wrap s around to 00h for the next byte and writing continues until the master sends a reset pulse. the write application register command can b e used as long as the application register has not yet been locked. if issued for a device with the application register locked, the data written to the register scratchpad will be lost. read status register [66h] the status register is a means for the m aster to find out whether the application register has been programmed and locked. after issuing the read status register command, the master must provide the validation key 00h before receiving status information. the two least significant bits of the 8 -b it status register are 0 if the application register was programmed and locked; all other bits always read 1. the master may finish the read status command by sending a reset pulse at any time. not recommended for new designs
ds2430a 8 of 19 memory function flow chart figure 6 (cont inued) read app lication register [c3h] this command is used to read the application register or the register scratchpad. as long as the application register is not yet locked, the ds2430a transmits data from the register scratchpad. after the application register is lock ed the ds2430a transmit s data from the application register, making the register scratchpad inaccessible for reading. the contents of the status register indicate where the data received with this command came from. after issuing the read application register command, the master must provide the 1 - byte starting address from where data is to be read. the ds2430a automatically increment s the address after every byte read by the master. after the data at address 07h has been read, the address counter wrap s ar ound to 00h for the next byte and reading continues until the master sends a reset pulse. copy & lock application register [5ah] after the data stored in the register scratchpad has been verified the master may send the copy & lock application register co mmand followed by a validation key of a5h to transfer the contents of the entire register scratchpad to the application register and to simultaneously write - protect it. the master may cancel this command by sending a reset pulse instead of the validation k ey. after the validation key is transmitted, the data line must be held above v pupmin for at least t prog . once t prog has expired, the application register will contain the data of the register scratchpad. further write accesses to the application register will be denied. the copy & lock application register command can only be executed once. not recommended for new designs
ds2430a 9 of 19 1- wire bus system the 1 - wire bus is a system that has a single bus master and one or more slaves. in all instances, the ds2430a is a slave device. the bus master is typically a microcontroller. the discussion of this bus system is broken down into three topics: hardware configuration, transaction sequence, and 1 - wire signaling (signal type and timing). the 1- wire protocol defines bus transactions in terms of the bus stat e during specified time slots that are initiated on the falling edge of sync pulses from the bus master. hardware configuration the 1 - wire bus has only a single line by definition; it is important that each device on the bus be able to drive it at the appropriate time. to facilitate this, each device attached to the 1 - wire bus must have open drain connection or three - state outputs. the 1 - wire port of the ds2430a is open drain with an internal circuit equivalent to that shown in figure 7. a multidrop bus c onsists of a 1 - wire bus with multiple slaves attached. the ds2430a communicates at regular 1 - wire speed, 1 5 .3kbits per second, and requires a pullup resistor as shown in figure 7. the idle state for the 1 - wire bus is high. if for any reason a transaction n eeds to be suspended, the bus must be left in the idle state if the transaction is to resume. if this does not occur and the bus is left low for more than 120s, one or more of the devices on the bus may be reset. hardware configuration figure 7 note: depending on the 1 - wire communication speed and the bus characteristics, the optimal pullup resistor value will be in the 0.3k ? to 2.2k ? range. to write to a single device, a r pupmax resistor and v pup of at least 4.0v is suffi cient. for writing multiple ds2430as simultaneously or operation at low v pup , the resistor should be bypassed by a low - impedance pullup to v pup while the device copies the scratchpad to eeprom. r pu r pu i l not recommended for new designs
ds2430a 10 of 19 rom functions flow chart figure 8 not recommended for new designs
ds2430a 11 of 19 transaction sequence the sequence for accessing the ds2430a via the 1 - wire port is as follows: ? initialization ? rom function command ? memory function command ? transaction/data initialization all transactions on the 1 - wire bus begin with an initialization sequence. the initializa tion sequence consists of a reset pulse transmitted by the bus master followed by a presence pulse(s) transmitted by the slave(s). the presence pulse lets the bus master know that the ds2430a is on the bus and is ready to operate. for more details, see the 1 - wire signaling section. rom function commands once the bus master has detected a presence pulse , it can issue one of the four rom function commands. all rom function commands are 8 bits long. a list of these commands follows (refer to flowchart in fig ure 8): read rom [33h] this command allows the bus master to read the ds2430as 8 - bit family code, 48 - bit serial number, and 8- bit crc. this command can be used only if there is a single ds2430a on the bus. if more than one slave is present on the bus, a data collision will occur when all slaves try to transmit at the same time (open drain produce s a wired - and result). the resultant family code and 48 - bit serial number usually result in a mismatch of the crc. match rom [55h] the match rom command, followe d by a 64 - bit rom sequence, allows the bus master to address a specific ds2430a on a multidrop bus. only the ds2430a that exactly matches the 64 - bit rom sequence will respond to the subsequent memory function command. all slaves that do not match the 64 -bi t rom sequence will wait for a reset pulse. this command can be used with a single or multiple devices on the bus. skip rom [cch] this command can save time in a single - drop bus system by allowing the bus master to access the memory functions without prov iding the 64 - bit rom code. if more than one slave is present on the bus and a read command is issued following the skip rom command, data collision will occur on the bus as multiple slaves transmit simultaneously (open drain pulldowns produce s a wired - and result). search rom [f0h] when a system is initially brought up, the bus master might not know the number of devices on the 1 - wire bus or their 64 - bit rom codes. the search rom command allows the bus master to use a process of elimination to identify the 64- bit rom codes of all slave devices on the bus. the search rom process is the repetition of a simple, three - step routine: read a bit, read the complement of the bit, then write the desired value of that bit. the bus master performs this simple, three - ste p routine on each bit of the rom. not recommended for new designs
ds2430a 12 of 19 after one complete pass, the bus master knows the contents of the rom in one device. the remaining number of devices and their rom codes may be identified by additional passes. see application note 187 for a comprehensive discussion of a search rom, including an actual example. 1- wire signaling the ds2430a requires strict protocols to insure data integrity. the protocol consists of four types of signaling on one line: reset sequence with reset pulse and presence pulse, wri te - 0, write - 1 and read - data. all these signals (except presence pulse) are initiated by the bus master. to get from idle to active, the voltage on the 1 - wire line needs to fall from v pup below the threshold v tl . to get from active to idle, the voltage nee ds to rise from v ilmax past the threshold v th . the time it takes for the voltage to make this rise is seen in figure 9 as , and its duration depends on the pullup resistor (r pup ) used and the capacitance of the 1 - wire network attached. the voltage v ilmax is relevant for the ds2430a when determining a logical level, not triggering any events. figure 9 shows the initialization sequence required to begin any communication with the ds2430a . a reset pulse followed by a presence pulse indicates the ds 2430a is r eady to receive data, given the correct rom and memory function command. if the bus master uses slew - rate control on the falling edge, it must pull down the line for t rstl + t f to compensate for the edge. after the bus master has released the line it goes into receive mode. now the 1 - wire bus is pulled to v pup through the pullup resistor. when the threshold v th is crossed, the ds 2340a waits for t pdh and then transmits a presence pulse by pulling the line low for t pdl . to detect a presence pulse, the maste r must test the logical state of the 1 - wire line at t msp . the t rsth window must be at least the sum of t pdhmax , t pdlmax , and t recmin . immediately after t rsth is expired, the ds 2430a is ready for data communication. initialization procedure reset and pres ence pulses figure 9 read/write time slots data communication with the ds 2430a takes place in time slots, which carry a single bit each. write time slots transport data from bus master to slave. read time slots transfer data from slave to master. figure 1 0 illustrates the definitions of the write and read time slots. all communication begins with the master pulling the data line low. as the voltage on the 1 - wire line falls below the threshold v tl , the ds 2430a starts its int ernal timing generator that determines when the data line is sampled during a write time slot and how long data is valid during a read time slot. resistor master ds2430a t rstl t pdl t rsth t pdh master tx reset pulse master rx presence pulse v pup v ihmaster v th v tl v ilmax 0v t f t rec t msp not recommended for new designs
ds2430a 13 of 19 master -to-slave for a write -1 time slot, the voltage on the data line must have crossed the v th threshold bef ore the write -1 low time t w1lmax is expired. for a write -0 time slot, the voltage on the data line must stay below the v th threshold until the write -0 low time t w0lmin is expired. for the most reliable communication, the voltage on the data line should not exceed v ilmax during the entire t w0l or t w1l window. after the v th threshold has been crossed, the ds 2430a needs a recovery time t rec before it is ready for the next time slot. read/write timing diagram figure 10 write - 1 time slot write -0 time slot read -data time slot resistor master t rec v pup v ihmaster v th v tl v ilmax 0v t f t slot t w0l resistor master v pup v ihmaster v th v tl v ilmax 0v t f t slot t w1l resist or master ds2430a t rec v pup v ihmaster v th v tl v ilmax 0v master sampling window t f t slot t rl t msr not recommended for new designs
ds2430a 14 of 19 slave -to- master a read -data time slot begins like a write -1 time slot. the voltage on the data line must remain below v tl until the read low time t rl is expired. during the t rl window, when responding with a 0, the ds 2430a starts pulling the data line low; its internal timing generator determines when this pulldown ends and the voltage starts rising again. when responding with a 1, the ds 2430a does no t hold the data line low at all, and the voltage starts rising as soon as t rl is over. the sum of t rl + (rise time) on one side and the internal timing generator of the ds 2430a on the other side define the master sampling window (t msrmin to t msrmax ) in which the master must perform a read from the data line. for the most reliable communication, t rl should be as short as permissible, and the master should read close to but no later than t msrmax . after reading from the data line, the master must wait until t slot is expired. this guarantees sufficient recovery time t rec for the ds 2430a to get ready for the next time slot. note that t rec specified herein applies only to a single ds 2430a attached to a 1 - wire line. for multidevice configurations, t rec must be e xtended to accommodate the additional 1 - wire device input capacitance. alternatively, an interface that performs active pullup during the 1 - wire recovery time such as the ds2482 - x00 or ds2480b 1 - wire line drivers can be used. improved network behavior (sw itchpoint hysteresis) in a 1 - wire environment, line termination is possible only during transients controlled by the bus master (1 - wire driver). 1 - wire networks, therefore, are susceptible to noise of various origins. depending on the physical size and to pology of the network, reflections from end points and branch points can add up, or cancel each other to some extent. such reflections are visible as glitches or ringing on the 1 - wire communication line. noise coupled onto the 1- wire line from external sou rces can also result in signal glitching. a glitch during the rising edge of a time slot can cause a slave device to lose synchronization with the master and, consequently, result in a search rom command coming to a dead end or cause a device - specific func tion command to abort. for better performance in network applications, the ds 2430a uses a new 1 - wire front end, which makes it less sensitive to noise. the 1 - wire front end of the ds 2430a differs from traditional slave devices in three characteristics. 1) the re is additional low - pass filtering in the circuit that detects the falling edge at the beginning of a time slot. this reduces the sensitivity to high - frequency noise. 2) there is a hysteresis at the low - to - high switching threshold v th . if a negative glitch crosses v th but does not go below v th - v hy , it will not be recognized (figure 1 1 , case a).. 3) there is a time window specified by the rising edge hold - off time t reh during which glitches are ignored, even if they extend below v th - v hy threshold (figure 1 1, case b, t gl < t reh ). deep voltage droops or glitches that appear late after crossing the v th threshold and extend beyond the t reh window cannot be filtered out and are taken as the beginning of a new time slot (figure 1 1 , case c, t gl t reh ). devices that have the parameters v hy , and t reh specified in their electrical characteristics use the improved 1 - wire front end. noise suppression scheme figure 11 v pup v th v hy 0v t reh t gl t reh t gl case a case c case b not recommended for new designs
ds2430a 15 of 19 memory function example example: write 2 data bytes to data memory locati on s 0006h and 0007 h . read entire data memory. master mode data (lsb first) comments tx reset reset pulse (480 s to 960s) rx presence presence pulse tx cch issue skip rom command tx 0fh issue write scratchpad command tx 06h start address = 06h t x <2 data bytes> write 2 bytes of data to scratchpad tx reset reset pulse rx presence presence pulse tx cch issue skip rom command tx aah issue read scratchpad command tx 06h start address = 06h rx <2 data bytes> read scratchpad data and verify tx reset reset pulse rx presence presence pulse tx cch issue skip rom command tx 55h issue copy scratchpad command tx a5h validation key tx data line must be above v pupmin for t prog . tx reset reset pulse rx presence presence pu lse tx cch issue skip rom command tx f0h issue read memory command tx 00h start address = 00h rx <32 bytes> read eeprom data page tx reset reset pulse rx presence presence pulse not recommended for new designs
ds2430a 16 of 19 absolute maximum ratings voltage range on data to ground - 0.5v to +6.0v data sink current 20ma operating temperature range - 40c to +85c junction temperature +150c storage temperature range - 55c to +125c lead temperature (soldering , 10s) +300c soldering temperature (reflow) tsoc +260c to -92 +250c stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational se ctions of the specifications is not implied. exposure to the absolute maximum rating conditions for extended periods may affect device reliability. electrical characteristics (t a = - 40 c to +85 c , unless otherwise noted.) ( note 1 ) parameter symbol conditions min typ max units data pin general data 1 - wire pullup voltage v pup (notes 2) 2.8 5.25 v 1 - wire pullup resistance r pup (notes 2, 3) 0.3 2.2 k ? input capacitance c io (notes 4, 5) 1000 pf input load current i l data pin at v pup 0. 05 15 a high - to - low switching threshold v tl (notes 5, 6, 7) 0.46 v pup - 1.8v v input low voltage v il (notes 2, 8) 0.5 v low - to - high switching threshold v th (notes 5, 6, 9) 1.0 v pup - 1.1v v switching hysteresis v hy (notes 5, 6, 10) 0.21 1.70 v ou tput low voltage v ol at 4ma (note 11) 0.4 v recovery time t rec r pup = 2.2k ? (notes 2,12) 5 s rising - edge hold - off time t reh (notes 5, 13) 0.5 5.0 s timeslot duration t slot (notes 2, 14) 65 s data pin, 1 - wire reset, presence detect cycle reset low time t rstl (note 2) 480 960 s presence detect high time t pdh 15 60 s presence detect low time t pdl 60 240 s presence detect sample time t msp (notes 2, 15) 60 75 s data pin, 1 - wire write write - 0 low time t w0l (notes 2, 16) 60 120 - s write - 1 low time t w1l (notes 2, 16) 1 15 - s data pin, 1 - wire read read low time t rl (notes 2, 17) 1 15 - s read sample time t msr (notes 2, 17) t rl + 15 s eeprom programming current i prog (notes 5, 18) 0.5 ma pro gramming time t prog (note 19) 10 ms write/erase cycles (en durance) (notes 20, 21) n cy at 25c 200k ? at 85c (worst case) 50k data retention (notes 22, 23 , 24 ) t dr at 85c (worst case) 40 years not recommended for new designs
ds2430a 17 of 19 electrical characteristics (continued) (t a = - 40 c to +85 c , unless otherwise noted.) ( note 1) note 1: limits are 100% production tested at t a = +25c and/or t a = +85c. limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization. typical values are not guaranteed. note 2: system requirement. note 3: maximum allowable pullup resistance is a function of the number of 1 - wire devices in the system and 1 - wire recovery times. the specified value here applies to systems with only one device and with the minimum t rec . for more heavily loaded systems, an active pullup such as that found in the ds2482 - x00, ds2480b, or ds2490 may be required. if longer t re c is used, higher r pup values may be able to be tolerated. note 4: maximum value represents the internal parasite capacitance when v pup is first applied. if a 2.2k ? resistor is used to pull up the data line, 2.5s after v pup has been applied the parasite capacitance will not affect normal communications. note 5: guaranteed by design, characterization and/or simulation only. not production tested. note 6: v tl , v th , and v hy are a function of the internal supply voltage which is itself a function of v pup , r pup , 1 - wire timing, and capacitive loading on data. lower v pup , higher r pup , shorter t rec , and heavier capacitive loading all lead to lower values of v tl , v th , and v hy . note 7: voltage below which, during a falling edge on data, a logic 0 is detected. note 8: the voltage on data needs to be less or equal to v il(max) at all times the master is driving data to a logic - 0 level. note 9: voltage above which, during a rising edge on data, a logic 1 is detected. note 10: after v th is crossed during a risin g edge on data, the voltage on data has to drop by at least v hy to be detected as logic '0'. note 11: the i - v characteristic is linear for voltages less than 1v. note 12: applies to a single device attached to a 1 - wire line. note 13: the earliest recog nition of a negative edge is possible at t reh after v th has been reached on the preceding rising edge. note 14: defines maximum possible bit rate. equal to 1/(t w0l(min) + t rec(min) ). note 15: interval after t rstl during which a bus master is guaranteed t o sample a logic - 0 on data if there is a ds2430a present. minimum limit is t pdh(max) ; maximum limit is t pdh(min) + t pdl(min) . note 1 6 : in figure 10 represents the time required for the pullup circuitry to pull the voltage on data up from v il to v th . th e actual maximum duration for the master to pull the line low is t w1lmax + t f and t w0lmax + t f respectively. note 1 7 : in figure 10 represents the time required for the pullup circuitry to pull the voltage on data up from v il to the input high threshold of the bus master. the actual maximum duration for the master to pull the line low is t rlmax + t f . note 1 8 : current drawn from data during the eeprom programming interval. the pullup circuit on data during the programming interval should be such that the voltage at data is greater than or equal to v pupmin . if v pup in the system is close to v pupmin , a low - impedance bypass of r pup , which can be activated during programming, may need to be added. note 19 : interval begins t rehmax after the trailing rising edge on data for the last timeslot of the validation key for a valid copy sequence. interval ends once the device's self - timed eeprom programming cycle is complete and the current drawn by the device has returned from i prog to i l . note 2 0 : write - cycle endurance is degraded a s t a increases. note 2 1 : not 100% production - tested; guaranteed by reliability monitor sampling. note 2 2 : data retention is degraded as t a increases. note 2 3 : guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to data sheet limit at operating temperature range is established by reliability testing. note 24: eeprom writes can become nonfunctional after the data - retention time is exceeded. long - term storage at elevated temperatures is not rec ommended; the device can lose its write capability after 10 years at +125c or 40 years at +85c. not recommended for new designs
ds2430a 18 of 19 package information for the latest package outline information and land patterns (footprints) , go to www.ma xim- ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern no. 3 to - 92 (bulk) q3+1 21 - 0248 3 to - 92 (t&r) q3+4 21-0250 6 tsoc d6+1 21-0382 90-0321 not recommended for new designs
ds2430a 19 of 19 maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408 - 737 - 7600 ? 2012 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision date description pages changed 4/3/95 initial release 8/26/96 changed c - lea d package to tsoc package. deleted v ihmax specification value. note under certain low voltage conditions v ilmax may have to be reduced to as much as 0.5v to always guarantee a presence pulse. added to v il specification, changed v cc to v pup in note 6. various 3/26/97 changed touch memory to i button . various 12/8/98 programming time changed from 100ms to 10ms, change v dd to v pup , revised note below f igure 7, programming current changed from 600a to 500a, q op removed from ec table, deleted from note 5 and will remain valid for 14s minimum (15s total from falling edge on 1 - wire bus). endurance added to ec table with note the copy scratchpad takes 10 ms maximum, during which the voltage on the 1 - wire bus must not fall below 2.8v. various 1/20/99 chip scale package added to ordering information 1 5/20/99 deleted duplicate t pdl and contradicting t prog spec from ec table 15 10/21/99 template conversion, style changes (capitalization of command names, write - one to write - 1, write - zero to write - 0) all 2/2/02 part number corrections, style corrections, note below figure 7 revised explain - ing the appropriate r pup range, corrections in the memory functions example (removed read memory section at the beginning), changed solder spec from 260 c to jedec reference, added notes 11, 12, 13 to ec table, changed t rstlmax from 5000s to 960s, revised text of ec table note 8. various 11/1/05 nrfnd watermark added all 1/16/07 lead free part numbers added; added flip chip graphic with bump electric al assignment, orientation mark and marking ; added flip chip 56 - level drawing number , changed "chip scale" name to "flip chip"; replac ed references to the book of i button standards with the corresponding application notes. various 8/8/07 note on formed le ads for to - 92 trl and url to 56 - g0006 - 003 added, i lmin and i lmax spec values added to ec table. data retention added to ec table. 1, 15 4/10 ordering information for standard and flip chip versions deleted, pin assignment for flip chip version deleted, data rate changed from 16.3 kbps to 15.3 kbps . style corrections and minor text updates for clarification . new 1 - wire front end, improved eeprom and related ec table with notes . package information section added . 1 various 12- 14, 16-17 18 2/12 reformatted t he ordering information , deleted the reference to the ucsp package. 1 revised ec table notes 1 and 18 ; a dded the land pattern no. to the package information section. 17, 18 not recommended for new designs

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